1099 offres d'emploi Senior Digital Design Engineer - Flanders |
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Site source : Talent BE
Lieu : Leuven Flanders
Société : ICsense NV
Détail de l'offre : FSM design,..constrained randomized tests and to gather and interpret metrics such as code/condition/FSM/toggle/functional coverageYou have experience with digital synthesis,..
Postuler | Plus d'offres Senior Digital Design Engineer
Plus d'offres - Leuven |
Site source : Talent BE
Lieu : Leuven Flanders
Société : ICsense NV
Détail de l'offre : make area and power estimationsTechnical team lead for the digital content of mixed-signal ASICs including interaction with customers,..
Postuler | Plus d'offres Senior Digital Design Engineer
Plus d'offres - Leuven |
Site source : Talent BE
Lieu : Leuven Flanders
Société : ICsense NV
Détail de l'offre : The job location can be Leuven or Ghent.The Senior Digital Design Engineer is responsible for the study,..
Postuler | Plus d'offres Senior Digital Design Engineer
Plus d'offres - Leuven |
Site source : Talent BE
Lieu : Leuven Flanders
Société : ICsense NV
Détail de l'offre : attend and present at project/review meetings worldwideCoach junior engineers in design,..The job location can be Leuven or Ghent.The Senior Digital Design Engineer is responsible for the study,..
Postuler | Plus d'offres Senior Digital Design Engineer
Plus d'offres - Leuven |
Site source : Talent BE
Lieu : Leuven Flanders
Société : ICsense NV
Détail de l'offre : constrained randomized tests and to gather and interpret metrics such as code/condition/FSM/toggle/functional coverageYou have experience with digital synthesis,..
Postuler | Plus d'offres Senior Digital Design Engineer
Plus d'offres - Leuven |
Site source : Talent BE
Lieu : Leuven Flanders
Société : ICsense NV
Détail de l'offre : make area and power estimationsTechnical team lead for the digital content of mixed-signal ASICs including interaction with customers,..
Postuler | Plus d'offres Senior Digital Design Engineer
Plus d'offres - Leuven |
Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : -MSEE or equivalent with min 3 to 5 years industrial experience-Solid grasp of simulation concepts such as regression testing,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : As part of our Digital Design team,..selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant d..
Postuler |
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Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : preparation of technical reviews and product/block documentationCollaboration with the backend team to analysis and optimize the design in terms of timing,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : ..As part of our Digital Design team,..presentation and team leading skillsStrong understanding of ASIC design flowStrong Experience with RTL coding in VHDL and/or Verilog/System VerilogStrong Experience with EDA tools (simulation,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : preparation of technical reviews and product/block documentationCollaboration with the backend team to analysis and optimize the design in terms of timing,..
Postuler |
Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : …-Good knowledge of Verilog and SystemVerilog for design and verification-Experience with RTL lint-Knowledgeable about DFT and ATPG-Knowledgeable about CDC issues and techniques for low power design-Experience with delay annotated gatelevel simulation-Experience with implem..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : As part of our Digital Design team,..presentation and team leading skillsStrong understanding of ASIC design flowStrong Experience with RTL coding in VHDL and/or Verilog/System VerilogStrong Experience with EDA tools (simulation,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : presentation and team leading skillsStrong understanding of ASIC design flowStrong Experience with RTL coding in VHDL and/or Verilog/System VerilogStrong Experience with EDA tools (simulation,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : presentation and team leading skillsStrong understanding of ASIC design flowStrong Experience with RTL coding in VHDL and/or Verilog/System VerilogStrong Experience with EDA tools (simulation,..
Postuler |
Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : …-Good knowledge of Verilog and SystemVerilog for design and verification-Experience with RTL lint-Knowledgeable about DFT and ATPG-Knowledgeable about CDC issues and techniques for low power design-Experience with delay annotated gatelevel simulation-Experience with implem..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant digital design experienceStrong communica..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant digital design experienceStrong communica..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant digital design experienceStrong communica..
Postuler |
Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : Belgium The Senior Digital Design & Verification Engineer has the following responsibilities:-Integrate legacy control and data path designs in new products-Update and verify legacy designs to fit new product requirements-Design and verify n..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant digital design experienceStrong communica..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : ..As part of our Digital Design team,..preparation of technical reviews and product/block documentationCollaboration with the backend team to analysis and optimize the design in terms of timing,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : As part of our Digital Design team,..selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant d..
Postuler |
Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : …-Good knowledge of Verilog and SystemVerilog for design and verification-Experience with RTL lint-Knowledgeable about DFT and ATPG-Knowledgeable about CDC issues and techniques for low power design-Experience with delay annotated gatelevel simulation-Experience with implem..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : preparation of technical reviews and product/block documentationCollaboration with the backend team to analysis and optimize the design in terms of timing,..
Postuler |
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