51 offres d'emploi Physical ASIC Design Implementation Engineer - Flanders |
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Site source : Talent BE
Lieu : Leuven Flanders
Société : imec
Détail de l'offre : You will work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out,..
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Site source : Talent BE
Lieu : Leuven Flanders
Société : imec
Détail de l'offre : SI)IPO’s (in-place optimization) to get the timing in all corners correctSolve setup & hold violationsSign-off extraction (SPEF)Sign-off timing (TEMPUS)Sign-off Power analysis (VOLTUS)Physical verification (DRC,..
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Site source : Talent BE
Lieu : Leuven Flanders
Société : imec
Détail de l'offre : For the further extension of the physical digital implementation group (Back-End group) in -link,..we are looking for a highly motivated engineer.-link,..
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Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : UVM,..Belgium/RemoteStart:..ASIC Design & Verification EngineerJob Type:..assertions,..ASAPResponsibilities- Integrate legacy control and data path designs in new products- Update and verify legacy designs to fit new product requirements- Design an..
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Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : …- Good knowledge of Verilog and SystemVerilog for design and verification- Experience with RTL lint- Knowledgeable about DFT and ATPG- Knowledgeable about CDC issues and techniques for low power design- Experience with delay annotated gatelevel simulation- Experience with ..
Postuler |
Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : …- Good knowledge of Verilog and SystemVerilog for design and verification- Experience with RTL lint- Knowledgeable about DFT and ATPG- Knowledgeable about CDC issues and techniques for low power design- Experience with delay annotated gatelevel simulation- Experience with ..
Postuler |
Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : …- Good knowledge of Verilog and SystemVerilog for design and verification- Experience with RTL lint- Knowledgeable about DFT and ATPG- Knowledgeable about CDC issues and techniques for low power design- Experience with delay annotated gatelevel simulation- Experience with ..
Postuler |
Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : ASAPResponsibilities- Integrate legacy control and data path designs in new products- Update and verify legacy designs to fit new product requirements- Design and verify new ultra-high speed DSP blocks for next gen products- Interface with the physical implem..
Postuler |
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Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : …- Good knowledge of Verilog and SystemVerilog for design and verification- Experience with RTL lint- Knowledgeable about DFT and ATPG- Knowledgeable about CDC issues and techniques for low power design- Experience with delay annotated gatelevel simulation- Experience with ..
Postuler |
Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : ASAPResponsibilities- Integrate legacy control and data path designs in new products- Update and verify legacy designs to fit new product requirements- Design and verify new ultra-high speed DSP blocks for next gen products- Interface with the physical implem..
Postuler |
Site source : Talent BE
Lieu : Flemish Brabant Flanders
Société : microTECH Global Ltd
Détail de l'offre : …- Good knowledge of Verilog and SystemVerilog for design and verification- Experience with RTL lint- Knowledgeable about DFT and ATPG- Knowledgeable about CDC issues and techniques for low power design- Experience with delay annotated gatelevel simulation- Experience with ..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant digital design experienceStrong communication,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : etc.)Experience with basic C/C++ programminghas context menuParagraphSkills & ExperienceCodage RTL,..As part of our Digital Design team,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : etc.)Experience with basic C/C++ programminghas context menuParagraphSkills & ExperienceApplication-Specific Integrated Circuit (ASIC) Development,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : As part of our Digital Design team,..Développement de circuits intégrés spécifiques à l’application (ASIC),..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : etc.)Experience with basic C/C++ programminghas context menuParagraphSkills & ExperienceCodage RTL,..you’ll take imaginative ideas and turn them into reality.ResponsibilitiesArchitecture/Micro-architecture specification developmentRTL implementation using VHDL or Verilog/Sy..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant digital design experienceStrong communication,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : Développement de circuits intégrés spécifiques à l’application (ASIC),..you’ll take imaginative ideas and turn them into reality.ResponsibilitiesArchitecture/Micro-architecture specification developmentRTL implementation using VHDL or Verilog/System VerilogLint,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : ..As part of our Digital Design team,..selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant digital <..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : presentation and team leading skillsStrong understanding of ASIC design flowStrong Experience with RTL coding in VHDL and/or Verilog/System VerilogStrong Experience with EDA tools (simulation,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : ....Développement de circuits intégrés spécifiques à l’application (ASIC),..simulation,..formal verification,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : you’ll take imaginative ideas and turn them into reality.ResponsibilitiesArchitecture/Micro-architecture specification developmentRTL implementation using VHDL or Verilog/System VerilogLint,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : you’ll take imaginative ideas and turn them into reality.ResponsibilitiesArchitecture/Micro-architecture specification developmentRTL implementation using VHDL or Verilog/System VerilogLint,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : etc.)Experience with basic C/C++ programminghas context menuParagraphSkills & ExperienceApplication-Specific Integrated Circuit (ASIC) Development,..
Postuler |
Site source : Talent BE
Lieu : Leuven Flanders
Société : Cyient
Détail de l'offre : you’ll take imaginative ideas and turn them into reality.ResponsibilitiesArchitecture/Micro-architecture specification developmentRTL implementation using VHDL or Verilog/System VerilogLint,..
Postuler |
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